--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   10:49:35 06/06/2010
-- Design Name:   
-- Module Name:   C:/Users/Tom/Documents/lcpd-scope/vhdl/project/Samples_to_Ram_Tb.vhd
-- Project Name:  LCPD_Scope
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Samples_to_Ram
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY Samples_to_Ram_Tb IS
END Samples_to_Ram_Tb;
 
ARCHITECTURE behavior OF Samples_to_Ram_Tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Samples_to_Ram
    PORT(
         Data_A_in : IN  std_logic_vector(11 downto 0);
         Data_B_in : IN  std_logic_vector(11 downto 0);
         newdata_in : IN  std_logic;
         Trigger_in : IN  std_logic;
         Run_in : IN  std_logic;
         reset : IN  std_logic;
         adr_out : OUT  std_logic_vector(11 downto 0);
         data_out : OUT  std_logic_vector(31 downto 0);
         we : OUT  std_logic;
         ena : OUT  std_logic;
         clk_out : OUT  std_logic;
         n_samples : IN  std_logic_vector(11 downto 0);
         n_presamples : IN  std_logic_vector(11 downto 0);
         trigger_out : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal Data_A_in : std_logic_vector(11 downto 0) := (others => '0');
   signal Data_B_in : std_logic_vector(11 downto 0) := (others => '0');
   signal newdata_in : std_logic := '0';
   signal Trigger_in : std_logic := '0';
   signal Run_in : std_logic := '0';
   signal reset : std_logic := '0';
   signal n_samples : std_logic_vector(11 downto 0) := (others => '0');
   signal n_presamples : std_logic_vector(11 downto 0) := (others => '0');

 	--Outputs
   signal adr_out : std_logic_vector(11 downto 0);
   signal data_out : std_logic_vector(31 downto 0);
   signal we : std_logic;
   signal ena : std_logic;
   signal clk_out : std_logic;
   signal trigger_out : std_logic;

   -- Clock period definitions
 --  constant clk_out_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Samples_to_Ram PORT MAP (
          Data_A_in => Data_A_in,
          Data_B_in => Data_B_in,
          newdata_in => newdata_in,
          Trigger_in => Trigger_in,
          Run_in => Run_in,
          reset => reset,
          adr_out => adr_out,
          data_out => data_out,
          we => we,
          ena => ena,
          clk_out => clk_out,
          n_samples => n_samples,
          n_presamples => n_presamples,
          trigger_out => trigger_out
        );

   -- Clock process definitions
   newdata_in_process :process
   begin
		newdata_in <= '0';
		wait for 5 ns;
		newdata_in <= '1';
		wait for 5 ns;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ms.
      Data_A_in <= "101010101010";	
		Data_B_in <= "010101010101";
		
		n_samples <= "000000000010";
		n_presamples <="000000000001"; 
		Run_in <= '1';
		
      wait for 100 ns;

      -- insert stimulus here 

      wait;
   end process;

END;
